• Analog Input
  • Supported Detector: SiPIN, SDD, HpGE
  • BNC connector
  • Single ended, AC coupled
  • Pulsed reset preamplifiers supported
  • Impedance: 50 Ohm / 1 kOhm (sw selectable)
  • 5/10V input ramp range
  • Programmable 4-step analog coarse gain: 2, 5, 15, 50
  • Shaper amplifier: 600ns for high rate applications or 100µs for high resolution measurament
  • Trimmer to compensate the preamplifier zero
  • Programmable fine gain: 0...10
  • Programmable DC offset adjustment on the input in the full scale range

• Detector Bias:
  • 80...250V Power Supply
  • Less then 1mVpp ripple
  • 100mV accurancy
  • Detector peltier control, up to 5V, 2A
  • Detector temperature monitor

• ADC:
  • Resolution: 14 bits
  • Sampling rate: 150 MS/s

• Digital Signal Processing:
  • Trigger with advanced noise rejection algorithm based on second derivate of the signal
  • Manual and automated Pole-Zero cancellation; decay time up to 0.65 ms
  • Pile-up rejection and Live Time correction
  • Digital fine gain
  • Trapezoidal shaper: up to 60µs peaking time
  • Baseline restorer with programmable averaging
  • Adjustable moving average low pass filter to reduce the high frequency noise

• Operating Modes:
  • Pulse Height Analysis (PHA): 16k-channel pulse height histogram internally built up; 1k-2k-4k-8k-16k rebin options at software level
  • Oscilloscope mode for waveforms monitoring

• Trigger Modes:
  • Internal trigger

• Communication interface:
  • USB 2.0 compliant

• MISC:
  • Firmware can be upgraded via USB
  • C/C++ library Windows and Linux
  • .NET (VB.NET) open source Demo Software
  • Supported by Sinerlab SinRX software
  • Dimensions: 106 W x 38 H x 128 L mm³
  • Weight: 300g

The digitized signal is sent to a programmable decimator that enables the instrument to implement filters with a length up to 64 µs. The output of the decimation stage is then deconvolved by a three zeros digital deconvolutor circuit. An innovative algorithm automatically calculates the poles of the input signal to find the best zeros position on the z-plane. The deconvolved signal is split and sent to the triggering and processing units. The trigger circuit consists of a fast trapezoidal filter with discrimination. The signal is simultaneously processed by an energy filter with programmable trapezoidal shape that lasts from 40 ns to 40 µs. Pileup and saturation circuit are also implemented. The reference level (baseline) of the pulses is estimated and subtracted to the corresponding energy measure. The corrected energy values are collected in a histogram of 16k channels into the FPGA device. The FPGA is connected both to a microcontroller and to a USB interface. The microcontroller is devoted to managing the Ethernet LAN and WiFi.

The trapezoidal digital filter offer significantly enhanced throughputs and achieve energy resolutions comparable to analog systems. The DPP2570 has been tested with an Amptek SiPM 13mm XR-100CR detector. A Am241 source has been used to generate the following spectrum. The resolution on 13.95KeV peak is about 2%, that is comparable with the intrinsic detector resolution.